The present invention relates to a storage circuit and a semiconductor memory device.
At present, as typical large-capacity semiconductor memory devices, a DRAM (Dynamic Random Access Memory) and a flash memory are named. In future, when pursuing further minuteness, and when trying to achieve reduction of bit cost and high performance, there are problems to be solved in each of these aspects. As regards further minuteness of the DRAM, a problem exists in measures for the structure of a capacity section, which results from the fact that the current DRAM adopts a cell structure of one transistorxe2x80x94one capacitor. To be more specific, the problem relates to the measures for the so-called stacked structure, in which for example, a capacity section is laminated on a substrate.
At present, the flash memory also has a problem of compatibility between minuteness and a life of a data storage period. Under the present circumstances, the flash memory is being developed with both of them as a backdrop. More specifically, the flash memory has the following principles of operation: during a write period, Fowler-Nordheim (FN)electric current is fed by means of a tunnel effect, or electric current is fed through an oxide film by a hot electron. Therefore, the electric current degrades the oxide flim, which places a limit on the number of times writing is allowed. In addition, it is not possible to scale the thickness of the oxide film in order to hold data. For these reasons, as described above, there is the problem of compatibility between minuteness and the life of a data storage period. Moreover, because the flash memory uses the same oxide film both for writing data and for data storage, the flash memory has also the disadvatage of compatibility between writing speed and a period during which data is held. Therefore, if the flash memory is used as a non-volatile memory, writing speed acnnot be increased under the present circumstances.
As a memory structure for solving the problems of the current large-capacity semiconductor memory, a PLED (Planar Localised Electron Device) is proposed. This can be found in, for example, reports at a symposium about VLSI technology in 1998, or the Japanese publication of patent applications (Japanese Patent Application Laid-Open No. Hei 10-200001, etc.). To be more specific, the examples at the symposium are the following: K. Nakazato et al., xe2x80x9cPLED-Planar Localised Electron Devicesxe2x80x9d, IEDM Tech. Dig., pp. 179-182, 1997; H. Mizuta et al., xe2x80x9cNormally-off PLED (planar Localised Electron Device) for non-volatile memory,xe2x80x9d Symposium on VLSI Technology Tech. Dig. 1998.
In the documents named above, a PLED element is integrated as a layered structure on a transistor, which is produced on a silicon substrate. Using this as a gain cell solves the problem of complication of DRAM cell capacity. In addition, the documents also describe the following: as a layered structure, separating a storage node from a pn junction enables dramatic reduction of leak electric current at the junction; because of it, application as a non-volatile memory such as the flash memory becomes possible.
As above, the large-capacity semiconductor memory was described. In the field where high speed is required, a SRAM, in which six transistors constitute a cell, is generally used. A requirement for a non-volatile memory used for mobile apparatuses is high. However, as regards the conventional SRAM cell, in order to use the SRAM cell as a non-volatile memory, a combination of the SRAM cell with a battery backup is forced, which requires power consumption caused by leak electric current of a memory and a peripheral circuit.
An object of the present invention is to solve the problems of the prior art, and to provide a storage circuit or a flip-flop circuit, which has low power consumption, is non-volatile, and is high-speed. The present invention provides a SRAM cell that is low power consumption, non-volatile, and high-speed.
According to the present invention, it is possible to provide a low power consumption SRAM cell or a low power consumption flip-flop circuit, which is not provided by the prior art.
Moreover, another object of the present invention is to provide a non-volatile flip-flop that uses a low leak device as typified by the PLED element. Thus, in a state in which the power is supplied, having a node, which outputs stored information steadily, enables some circuit setting, and enables application as a Content Addressable Memory, etc.
A basic configuration according to the present invention is a storage circuit characterized by the following: said storage circuit has a semiconductor storage element, of which a memory node becomes low leakage, in a memory area; and said storage circuit has a second node, to which information stored in the first node is outputted steadily in a state in which power is supplied. In this case, the semiconductor storage element, of which a memory node is low leakage, means that a semiconductor storage element in which an interval of a holding operation of required storage information is long. If the interval of the holding operation of required storage information is, for example, one second or more (preferably, 10 seconds or more), it is suitable as the low leak semiconductor storage element according to the present invention. Moreover, if the interval of the holding operation of required storage information is about once a day or more, or about once a week or more, it is needless to say that the element is more desirable.
One specific configuration example of the present invention is a storage circuit characterized by the following:
a storage element is a device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to a given voltage so that the second carrier is stored in the first node; and
said storage circuit comprises a second node, to which information stored in the first node is output steadily in a state in which power is supplied.
According to the storage circuit, it is possible to provide a non-volatile flip-flop circuit, which is capable of holding stored information even when the power supply is turned off. Moreover, according to the storage circuit, it is possible to provide a non-volatile SRAM (Static Random Access Memory), which is capable of holding stored information even when the power supply is turned off.
For purposes of providing the SRAM, it is desirable to configure a circuit according to the invention concepts, which will be described below. To be more specified, in the example, the low leak semiconductor element is built into a flip-flop; and a switch of the low leak semiconductor storage element is provided between a gate electrode of a drive transistor of the flip-flop and an output in phase with the gate electrode. Then, while writing and while data is being stored, the switch is turned ON or OFF. Thus, while writing data, an operation similar to that of the general SRAM is performed. In addition to it, while data is being stored, nonvolatility can also be achieve by shutting down the power supply.
A typical example of the semiconductor element for a switch, in which electric current is low leakage, is commonly called a PLED element. This PLED element is a semiconductor element comprising a layered structure of an insulated layer and a semiconductor layer, said semiconductor element is characterized by the following: the layered structure is placed between a first electrode and an electron storage node; and the layered structure controls electric current. As described above, this element itself can be found in, for example, the Japanese publication of patent applications (Japanese Patent Application Laid-Open No. Hei 10-200001).
In this case, in comparison with the present invention, the prior art will be considered as below. In general, the flip-flop circuit has a node that outputs stored information steadily in a state in which the power is supplied. Therefore, for example, using the value of the stored information enables some circuit setting, and enables use as a Content Addressable Memory. However, because a DRAM cell cannot output the stored information steadily, its application is limited. In addition, as regards a backup SRAM circuit that uses a conventional battery, power is always supplied to a memory circuit. Therefore, power consumption due to leak electric current of a memory cell and a peripheral circuit cannot be avoided. The present invention can eliminate these limits. In this connection, in the document, the Japanese publication of patent applications, and the like, which were described above, application of the PLED element as a large-capacity semiconductor memory is mentioned. However, application as a high-speed memory or a flip-flop is not included.
Next, main modes of the present invention will be listed as below. The modes will be described more specifically in xe2x80x9cBest Modes for Carrying out the Inventionxe2x80x9d.
(1) A first mode relates to a storage circuit comprising a flip-flop, wherein:
a storage element is a device comprising:
A first path for a carrier;
A first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node; and
said flip-flop has at least a second node, to which information stored in the first node is output steadily in a state in which power is supplied to the storage element.
(2) A second mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel;
between a gate electrode of a drive gate insulated field effect transistor for either of the first cross couple or the second cross couple and a node for outputting a voltage in phase with the gate electrode, there is a layered structure of an insulated layer and a semiconductor layer;
the layered structure is placed between a first electrode and an electron storage node; and
said flip-flop has at least a second node, to which information stored in the first node is outputted steadily in a state in which power is supplied to the storage element.
(3) A third mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel;
between a gate electrode of a drive gate insulated field effect transistor of the first cross couple, which uses the N type gate insulated field effect transistor, and a node for outputting a voltage in phase with the gate electrode, there is a layered structure of an insulated layer and a semiconductor layer;
the layered structure is placed between a first electrode and an electron storage node; and
said flip-flop has a semiconductor element, in which the layered structure controls electric current.
(4) A fourth mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel;
said flip-flop has a semiconductor storage element, in which stored information is low leakage, between a gate electrode of a drive gate insulated field effect transistor of the first cross couple, which uses the N type gate
insulated field effect transistor, and a node for outputting a voltage in phase with the gate electrode.
(5) A fifth mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
said flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor for either of the first cross couple or the second cross couple and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(6) A sixth mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
said flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor of the first cross couple, which uses the N type gate insulated field effect transistor, and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(7) A seventh mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said storage flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(8) An eighth mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said flip-flop has a semiconductor storage element, in which stored information is low leakage, between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode.
(9) An ninth mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode, there is a layered structure of an insulated layer and a semiconductor layer;
the layered structure is placed between a first electrode and an electron storage node; and
said flip-flop has a semiconductor element, in which the layered structure controls electric current.
(10) A tenth mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said flip-flop has a semiconductor storage element, in which stored information is low leakage, between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode.
(11) An eleventh mode relates to a storage circuit comprising a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
between a gate electrode of a drive gate insulated field effect transistor for either of the first cross couple or the second cross couple and a node for outputting a voltage in phase with the gate electrode, there is a layered structure of an insulated layer and a semiconductor layer;
the layered structure is placed between a first electrode and an electron storage node; and
said flip-flop has a semiconductor element, in which the layered structure controls electric current.
(12) A twelfth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
between a gate electrode of a drive gate insulated field effect transistor of the first cross couple, which uses the N type gate insulated field effect transistor, and a node for outputting a voltage in phase with the gate electrode, there is a layered structure of an insulated layer and a semiconductor layer;
the layered structure is placed between a first electrode and an electron storage node; and
said flip-flop has a semiconductor element, in which the layered structure controls electric current.
(13) A thirteenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
said flip-flop has a semiconductor storage element, in which stored information is low leak, between a gate electrode of a drive gate insulated field effect transistor of the first cross couple, which uses the N type gate insulated field effect transistor, and a node for outputting a voltage in phase with the gate electrode.
(14) A fourteenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
said flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor for either of the first cross couple or the second cross couple and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(15) A fifteenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel; and
said flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor of the first cross couple, which uses the N type gate insulated field effect transistor, and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(16) A sixteenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said storage flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(17) A seventeenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said flip-flop has a semiconductor storage element, in which stored information is low leakage, between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode.
(18) An eighteenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said storage flip-flop has a device between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode, said device comprising:
a first path for a carrier;
a first node for storing a charge that generates an electric field where conductivity of the first path is changed; and
a barrier structure through which a second carrier moves in response to given voltage so that the second carrier is stored in the first node.
(19) A nineteenth mode relates to a Static Random Access Memory device having a memory cell that comprises a flip-flop, wherein:
a first cross couple, which uses two N type gate insulated field effect transistors, and a second cross couple, which uses two P type gate insulated field effect transistors, are connected in parallel so that a first impurity area of the N type gate insulated field effect transistor is connected to a second impurity area of the P type gate insulated field effect transistor, and so that a gate electrode of the N type gate insulated field effect transistor is connected to a gate electrode of the P type gate insulated field effect transistor; and
said flip-flop has a semiconductor storage element, in which stored information is low leakage, between a gate electrode of a drive gate insulated field effect transistor for the first and the second cross couple and a node for outputting a voltage in phase with the gate electrode.